1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices employed in various computing devices, control equipment or the like, and a manufacturing method thereof.
2. Description of the Background Art
A non-volatile semiconductor memory device is used for writing/reading a piece of information, based on change in electric field effect to a channel portion caused by the electric charge in the floating gate, by applying a high voltage between a floating gate and a source or a drain, and injecting/pulling electric charge into/out from the floating gate. As the electric charge in the floating gate is isolated by an insulation film, it can be retained for a long time as non-volatile information even after the power-off.
A conventional non-volatile semiconductor memory device will be described with reference to FIG. 53.
On a floating gate fin electrode 509, a second gate insulation film 512 is formed and a control gate lower electrode 513 of polycrystalline silicon and a control gate upper electrode 514 of a metal silicide film are formed thereon. A control gate electrode 517 is formed of control gate lower electrode 513 and control gate upper electrode 514. Further on control gate upper electrode 514 of the metal silicide film, a hard mask 515 which serves as a mask at etching is formed of a silicon oxide film.
Bit lines are arranged among sources/drains from the back to the front and word lines are arranged from the right to the left in the drawing.
In FIG. 53, control gate electrode 517 and second gate insulation film 512 in the front section are not shown to allow the viewer to see a central trench portion. A structure shown in FIG. 53 is formed by etching control gate electrode 517 and second gate insulation film 512 using hard mask 515 of a silicon oxide film as a mask, removing a floating gate layer through anisotropic etching using control gate electrode 517 as a mask, and thereby forming a floating gate electrode 518. Here, a polycrystalline silicon residue which is an etching residue 519 is left on a side wall of an insulation film facing the central trench portion.
Another example where etching residue remains is shown in FIGS. 54 and 55. An end portion itself of a floating gate electrode 618 serves as a mask at a step formed by an end of floating gate electrode 618 and an isolating insulation film 602, and a polycrystalline silicon residue 619 is produced on a side wall of the step formed by isolating insulation film 602 and the end of the floating gate electrode as shown in FIG. 55.
Generally, in a non-volatile semiconductor memory device such as a flash memory, capacitance coupling ratio C2/(C1+C2) must be high. Here, capacitance C1 is capacitance between the floating gate electrode and a channel portion and capacitance C2 is coupling capacitance between the control gate electrode and the floating gate electrode. When voltage V is applied from an external source to the control gate electrode, potential on the floating gate electrode is C2/(C1+C2). Therefore, in order to apply a sufficiently high voltage on the floating gate electrode, a correspondingly high capacitance coupling ratio is required. The high capacitance coupling ratio allows an operation of non-volatile semiconductor memory device at a low voltage while securing a high floating gate potential.
To increase the capacitance coupling ratio, capacitance C2 between the control gate electrode and the floating gate electrode must be increased. Therefore, a fin electrode 509 is provided in an upper portion of the floating gate electrode thereby increasing the area between the floating gate electrode and the control gate electrode.
In the above described structure, some portions are undesirably masked from being etched at the anisotropic etching of floating gate electrode 518 of polycrystalline silicon or the like, and etching residue 519 tends to be produced along the side wall of the insulation film facing the trench portion. Such polycrystalline silicon residue forms short circuits between gate electrodes and as a result causes a significant yield reduction. In addition, even if etching selectivity between polycrystalline silicon and an underlying layer is made as high as possible to permit over-etching for the removal of the etching residue, there is a certain limitation in the etching selectivity and first gate insulation film 503 possibly be penetrated.
In addition, in non-volatile semiconductor memory devices such as a flash memory, for the increase in capacitance C2 between the floating gate electrode and the control gate electrode which in turn increases the above mentioned capacitance coupling ratio, an area of the floating gate electrode, especially width thereof must be increased. Conventionally, the width of the floating gate electrode is increased by providing fin electrode 509 up to about three times the length of the channel portion. Therefore, the area of the floating gate electrodes is increased and hinders the miniaturization of non-volatile semiconductor memory devices.